Buffer circuit for decoupling system interference

ABSTRACT

A transistorized input-output buffer magnetically coupled through a wall of a Faraday cage to isolate system components from field interference. The input buffer includes an oscillator circuit responsive to actuation of a process detector, a transformer having a primary winding connected to the oscillator output and a demodulator circuit within the cage having an input connected to the transformer secondary winding and an output connected to a digital processor. The output of the processor is connected to the output buffer which includes an oscillator circuit within the cage, a transformer having a primary winding connected to the oscillator output, and an amplifier connected to the transformer secondary winding for energizing actuators to control the process. The cores of the transformers for the input and output buffer circuits are positioned in an airgap formed in the wall of the Faraday cage in order to isolate the system components from electrostatic and electromagnetic interference.

0 United States Patent 1 2,753

[72] Inventors Jean C. Lejnn 2,914,719 11/1959 Walton etal. 336/84X Paris; 3,028,539 4/1962 Wright 336/84X Michel L. Herjean, LesClayes-Sous-Bois, 3,244,960 4/1966 Stevens et al. 321/8 both of, France 3,406,364 10/1968 Russell et al.... 336/84X [21] Appl. No. 794,702 3,465,232 9/1969 Weber 321/8 [22] Wed 1969 Primary Examiner-William M. Shoop, Jr. [45] Patented June 1, 1971 A" J h F L h [73] Assignee Controle Bailey Societe Anonyme omey o n u rs [32] Priority Feb. 7, 1968 [33] France [31] 139925 ABSTRACT: A transistorized input-output buffer magnetically coupled through a wall of a Faraday cage to isolate [54] BUFFER CIRCUIT FOR DECOUPUNG SYSTEM system components from field interference. The input buffer INTERFERENCE includes an oscillator circuit responsive to actuation of a rocess detector, a transformer having a primary winding congclmmssnrawmg nected to the oscillator output and a demodulator circuit [52] [1.8. CI 321/2, i i the cage having an input connected to the transformer 321/8, 336/84 secondary winding and an output connected to a digital [51] Int. Cl 02m 3/22 processeh The output f the processor is connected to the [50] Field of Search 321/2, 8; output g whieh includes an oscillator circuit within the 336/84 cage, a transformer having a primary winding connected to 56 R f Ced the oscillator output, and an amplifier connected to the trans- 1 e erences l former secondary winding for energizing actuators to control UNITED STATES PATENTS the process. The cores of the transformers for the input and 2,476,931 7/1949 Tubbs 321/8 output buffer circuits are positioned in an airgap formed in the 2,682,018 6/1954 Phillips.. 336/84X wall of the Faraday cage in order to isolate the system com- 2,904,762 9/ 1959 Schulz 336/84 ponents from electrostatic and electromagnetic interference.

PATENTEDJUN Han 3,582.753

SHEET 2 OF 6 PROCESSOR INVENTORS JEAN C..LEJON BY. MICZEL L. R EAN v ATTOR EY PATENTEDJUN H911 3.582.753

' SHEET 3 0F 6 INVENTORS JEAN C. LEJON BY MICHEL L. HERJEAN PATENTEB JUN um SHEEI S [if 6 INVENTORS JEAN C. LEJON BY MICHEL iguana T ORNEY mmm mmm w;

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ORNEY BUFFER CIRCUIT FOR DECOUPLING SYSTEM INTERFERENCE SUMMARY OF THE INVENTION In accordance with the invention, a transistorized input buffer circuit including an oscillator, a coupling transformer and a demodulator is connected on the oscillator-input side to a process detector and on the demodulator-input side to a process computer. The command signals from the logic process computer and connected to a transistorized output buffer circuit including an oscillator, a coupling transformer and either an AC or DC amplifier. The respective amplified signals are used to energize process control actuators. The oscillator of the input buffer circuit and the amplifier of the output buffer circuit are mounted outside a Faraday cage and the demodulator of the input buffer circuit and the oscillator of the output buffer circuit are mounted inside the Faraday cage to provide isolation from electrostatic and electromagnetic interference.

The principal object of the invention is to provide a static interface between the field components and the system components of an automatic process control system to isolate the system components from electrostatic and electromagnetic interference.

Another important object of the invention is to provide a modified Faraday cage for decoupling transistorized input and output buffer circuits.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a side elevational view illustrating an enclosure forming a Faraday cage for isolating system components from field components through a decoupling unit mounted on the cage wall.

FIG. 2 is a schematic illustration relating process detectors through input buffers, into a processor, then through output buffers to process actuators.

FIG. 3a is an enlarged perspective view of a decoupling unit shown in FIG. 1.

FIG. 3b is an enlarged perspective view of a mounting member used in the decoupling unit for the buffer circuits.

FIG. 4 is a schematic illustration of an embodiment of an input buffer circuit.

FIG. 5 is a schematic illustration of an embodiment of an output buffer circuit having an AC amplifier.

FIG. 6 is a partial schematic illustration of the embodiment of FIG. 5 having a DC amplifier.

FIG. 7 illustrates how the logic process circuits may be mounted to the enclosure.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now to the drawings, FIG. 1 shows an enclosure 100 including a Faraday cage defining a low-power compartment 104, one wall thereof forming a static buffer shield 103 to a high-power compartment 105 and also serving as a mounting support for a decoupling unit 4 (as shown enlarged in FIGS. 3a and 3b).

The mounting unit 4 includes a meal plate 408 to which is mounted a mounting member 405 for low-power input or output buffer circuits 110, 111, the mounting plate 408 also serving to mount mounting member 406 for high-power input or output buffer circuits 112, 113. The static buffer shield 103 is provided with a plurality of apertures 106. Circuit 112 is magnetically coupled to circuit 110, and circuit 113 is magnetically coupled to circuit 111 through one of the apertures 106. A more detailed description of the decoupling unit 4 will be given hereinafter.

A frame 116, located within the low-power compartment 104, serves as a mounting support for mounting boards 115, which may be of printed circuit design, and on which are mounted logic process circuits 114. An access door 101 is pro vided to the low-power compartment 104, and may also serve as. one wall of the Faraday cage. All of the walls of the low- :power compartment 104, including the access door 101, are

made of metal in order to form a Faraday cage for isolating the low-power components from electrostatic and electromag netic interference originating outside the low-power compartment 104. An access door 102 is also provided to the highpower compartment 105 in order to gain access to the components located in this compartment.

The static buffer shield 103 shown in FIG. 1 is provided with a plurality of apertures 106 which are rectangular in shape, and it should be understood that the apertures 106, located below the decoupling unit 4, may have decoupling units similar to decoupling unit 4 covering them. If the particular system does not require additional decoupling units like 4 to cover all of the apertures 106, then it is to be understood that the excess apertures 106 are to be covered with metal plates in order to preserve the continuity of the Faraday cage. The apertures 106, if reduced in size, would eliminate the requirement for mounting plate 408, and mounting members 405, 406 could be mounted directly to shield 103. It should also be understood that the low-power buffer circuits 110, 111 are either low-power input buffer circuits or low-power output buffer circuits, but may not be both input and output buffer circuits located on the same decoupling plate 408. Similarly, the circuits 112, 113 are either high-power input buffer circuits or high-power output buffer circuits, but may not be both input and output buffer circuits located on the same decoupling plate 408.

Referring now to FIG. 2, the drawing illustrates schematically the flow of information through a process control system. An input buffer circuit includes a field-input oscillator 2,, located in the high-power compartment 105, a system-input demodulator 3,, located in the low-power compartment 104, and an input ring core 4, passing through the static buffer shield 103 to provide magnetic coupling between the fieldinput oscillator 2, and the system-input demodulator 3,. Note that a plurality of field-input oscillators 2,2,,, located in the high-power compartment 105, are connected by input-ring cores 4,4,, to a plurality of system-input demodulators 3,- --3,,, respectively, in the low-power compartment.

An output buffer circuit comprises a system-output oscillator 5,, located in the low-power compartment 104, a field-output amplifier 6,, located in the high-power compartment 105, and an output-ring core 7, for magnetically coupling the system-output oscillator 5, to the field-output amplifier 6, through the static buffer shield 103. It should be noted that a plurality of system-output oscillators 5,5,, are located in the low-power compartment 104 and are magnetically coupled through output-ring cores 7,7,, to a plurality of field-output amplifiers 6,6,,, respectively, located in the high-power compartment 105.

FIG. 2 further illustrates that a plurality of process detectors 8,-8, are commonly connected to a detector supply 11 which provides the DC power for energizing the respective fieldinput oscillators 2,--2 through input lines 118,-1l8,,. A processor 10, including the logic process circuits 114 is connected to the system-input demodulators 3,3,,, and the out puts of the processor 10 are connected to the system-output oscillators 5,5,,. The field-output amplifiers 6,6,,, which are either DC or AC amplifiers, are connected to control actuators 9,-9,, through field-output lines ll9,1l9,,. The control actuators 9,-9,, are commonly connected to an actuator supply 12, which is shown as a DC power source but would be replaced by an AC power source when the amplifiers 6,6,, are AC amplifiers, to provide the power for the control actuators.

OPERATION OF THE PROCESS CONTROL SYSTEM The operation of the process control system illustrated in FIG. 2 will be described by tracing the flow of information from one of the process detectors 8, through the system to the associated control actuator 9,. The process detector 8, is shown as a normally open set of contacts. Assuming, for purposes of tracing the operation, that switch 8, is now closed, the

detector supply 11 provides DC power through input line 118, to the field-input oscillator 2,. The oscillator 2, is triggered into oscillation, and the oscillations are magnetically coupled through the ring core 4, into the system-input demodulator 3, which converts the oscillations into a DC signal which is connected to the input of processor 10. The processor produces a DC command signal based on the input information, and this command signal is connected to the output oscillator 51. The output oscillator 5, is triggered into oscillations, and these oscillations are magnetically coupled through the output ring core 7, into the field-output amplifier 6,. The field-outut amplifier 6, (using the embodiment shown in FlG. 6) converts the oscillations to an amplified DC voltage which is connected to control actuator 9, through the field-output line 119, and energizes control actuator 9, which takes the form of a relay coil. The actuator supply 12 supplies power to the load as shown in FIG. 6.

An alternative embodiment for the output buffer circuit is shown in FIG. 5 wherein an AC amplifier replaces the DC amplifier in order to provide an amplified AC voltage to control actuators 9,9,, respectively. lt should be understood that actuator supply 12, shown in FIG. 2 as a battery, is replaced with an AC actuator supply for this mode of operation.

THE DECOUPLING UNlT FIG. 3a shows an enlarged partial perspective view of the decoupling unit 4 shown in FIG. 1. The decoupling unit 4 includes a metal decoupling plate 408 which substantially covers the rectangular aperture 106 in the static buffer shield 103 partially shown in phantom. The decoupling plate 408 has a pair of tongue elements, each element being formed by a pair of spaced notches transverse to the longitudinal axis of the decoupling plate 408. One of the tongue elements 409 is exposed to view in the lower portion of FIG. 3a, and the other tongue element is hidden from view by a mounting member 405 in the upper portion of FIG. 3a. A transformer ring core 40 is mated with the tongue element 409 so that its axis is coincident with the axis of the tongue element 409 with a portion of the transformer 40 being disposed on each side of the decoupling plate 408.

Mounting members 405, 406, as shown in FlG. 3b, are fastened to each side of the decoupling plate 408. The mounting members 405, 406 each have a pair of apertures 407 which receive the portion of each transformer 40 projecting from the respective side of the decoupling plate 408. The mounting members 405, 406 are used to mount the decoupling circuit boards 401, 402 respectively, each having terminals 403, to the decoupling plate 408. Aligned screw holes 411 are provided in the decoupling circuit boards 401, 402, in the mounting members 405, 406 and in the decoupling plate 408 for the purpose of fastening these elements tog-ether. Attachment holes 410 in the decoupling plate 408 are aligned with holes in the static buffer shield 103, shown in phantom, in order to mount the decoupling unit 4. Another embodiment of the decoupling unit provides tongue elements like 409 directly in the static buffer shield 103 instead of apertures 106, and the mounting members 405, 406 are fastened directly to shield 103.

Two pair of clamping guides 412 project outwardly from the surface of each of the decoupling circuit boards 401, 402 to receive the edges of circuit boards 110, 111 and 112, 113. The circuit board 110 has a plurality of connectors extending toward the decoupling circuit board 401 which electrically connect with a plurality of connectors 404 projecting toward the circuit board connectors 201. A similar connector arrangement is provided for circuit boards 111, 112 and 113. The inputs and outputs to each circuit board are thus connected through the connectors 201 and 404 and terminate in the terminals 403 to which outside connections are made. The circuit boards 110 and 112, however, are magnetically coupled through a transformer 40 as is also true for circuit boards 111 and 113 as well as the other low-power to high-power or high-power to low-power circuit boards in the system.

Primary windings of transformer 40 are wound on the ring core of the transformer on one side of the metal decoupling plate 408, and the secondary windings are wound on the ring core on the other side of the decoupling plate 408. The relative size of the decoupling plate 408, with respect to aperture in the static buffer shield 103, is such as to cover the aperture between the lowpower compartment 104 and the high-power compartment with the exception of the remaining air space in the region of the tongue elements 409. The length of each tongue element 409 is slightly shorter than the length of each notch associated with it in order to prevent the end of the tongue element from touching the static buffer shield 103. With this configuration, it should be understood that if the decoupling plate 408 were mounted in position on the static buffer shield 103 without he transformer 40 inserted over the tongue element 409, a U-shaped airgap would result between the high-power compartment 105 and the low-power compartment 104 in the region of each tongue element 409. This airgap could also be provided directly through shield 103 thus eliminating plate 408. The airgap configuration insures maximum isolation between the compartments while preventing a magnetic short circuit between the end of the tongue element 409 and the static buffer shield 103. Another advantage of the decoupling unit 4 with plate 408 included, however, is ease of removal and replacement.

lNPUT BUFFER CIRCUIT Reffering now to FIG. 4, an input buffer circuit is schematically illustrated and includes an oscillator circuit 2 which is transfonner coupled to a demodulator circuit 3 through a decoupling unit 4. The oscillator circuit 2 is disposed in the high-power compartment 105 of the static buffer shield 103 and the demodulator circuit 3 is disposed in the low-power compartment 104. The input to the oscillator circuit 2 is connected across the field-input terminal 118 and ground terminal 120.

The oscillator circuit 2 includes a voltage dropping resistor 208 connected in series with the input terminal 118 and is also connected to a Zener diode 209, which has its anode terminal connected to ground 120. An electrolytic capacitor 210 is connected in parallel with the Zener diode 209, and a delay circuit, including a biasing resistor 21] in copies with an electrolytic capacitor 212, is connected substantially in parallel with the capacitor 210. An N-P-N transistor 204, having a base, b, an emitter, e, and a collector, c, has its base connected between the resistor 211 and capacitor 212. The emitter of transistor 204 is connected to ground through an automatic biasing circuit including a resistor 206 in parallel with a capacitor 207. The collector-emitter junction of transistor 204 is connected in series with a primary winding 41 of transformer 40 to the resistor 208. A capacitor 205 is connected across the collector-emitter junction of transistor 204 for eliminating high frequency oscillations.

The demodulating circuit 3 includes a secondary winding 42 of transformer 40 connected across a diode-type voltage doubler having a diode 301 connected in series with the secondary winding 42 and a capacitor 303 connected in series with diode 301; a reverse-poled diode 302 is connected in series with the secondary winding 42 of transformer 40 and also in series with capacitor 304. A summing capacitor 305 is connected in parallel across capacitors 303 and 304. One terminal of capacitor 305 is connected through diode 306, and the other terminal of capacitor 305 is connected to the negative terminal 318 of a DC voltage source. An N-P-N transistor 309 has its base terminal connected to the cathode of diode 306 and its emitter terminal connected to terminal 318. A resistor 307 in parallel with a capacitor 308, is connected between the base and emitter terminals of transistor 309. The collectoremitter junction of transistor 309 is connected in series with resistor 310 to terminal 315 which is the positive terminal of the voltage source having a negative terminal 318. Terminal 315 is also connected to resistor 312 which is connected to diode 311 which has its cathode connected to the collector terminal of transistor 309. The anode of diode 311 is connected to the anodes of diodes 313, 314 which have their cathodes connected to response terminal 317 and readout terminal 316 respectively.

A decoupling unit 4, like that shown in FIGS. 3a and 3b, is provided between the oscillator circuit 2 and the demodulator circuit 3 for isolation from interference. The demodulator circuit 3 is mounted inside of the Faraday cage as previously described.

Operation of Input Buffer Circuit The operation of the input buffer circuit illustrated in FIG. 4 is essentially the following series of events. A DC input voltage of at least 15 milijoules of power is applied across terminals 118-120 of the oscillator circuit 2. The dropping resistor 208 establishes a voltage level for Zener diode 209. Capacitor 210 charges through resistor 208, and taken together, these elements form a delay circuit for delaying the control voltage on the base of transistor 204. The combination of resistor 211 and capacitor 212 also introduces a delay into the control voltage to the base of transistor 204, and these two delay circuits are adjusted to give a total time delay of about 25 milliseconds. When the control voltage on the base of transistor 204 is positive with respect to the emitter bias voltage, the collector-emitter junction of transistor 204 is forward biased, and this causes an oscillating current to How in the primary winding 41 for transformer 40. The frequency of oscillations may be varied by adjusting the value of resistor 211 relative to the value of resistor 206.

The AC oscillations in the primary winding 41 are magnetically coupled to the secondary winding 42 through the transformer 40. During positive half-cycles of the oscillations, diode 301 is forward biased, and capacitor 303 is charged. During negative-half-cycles of the oscillations, the diode 302 becomes forward biased and charges capacitor 304, the series aiding connection of the capacitors 303 and 304 adding their voltages across capacitor 305. Diode 306 becomes forward biased and introduces a control voltage to the base of transistor 309. Resistor 307 and capacitor 308 provide the base-emitter bias for transistor 309. The collector-emitter junction of transistor 309 is nonconductive until the base of transistor 309 is positive with respect to the emitter. Therefore, preceeding the initiation of oscillations in oscillator circuit 2, transistor 309 was off, and the-collector-emitter junction of transistor 309 wasan open circuit. Diodes 313 and 314 were, at that time, forward biased into conduction from the application of positive voltage from terminal 315 through resistor 312. When the control voltage on the base of transistor 309 became positive with respect to the emitter voltage, the collector-emitter junction of transistor 309 became essentially a short circuit thereby causing the collector-emitter junction to become forward biased through resistors 310 and 312. The anodes of diodes 313, 314 are, therefore, no longer forward biased when transistor 309 becomes saturated. The outputs of the response terminal 317 and readout terminal 316 are, therefore, zero. The changed state of the response terminal 317 and readout terminal 316 supply information to the processor (shown in FIG. 2).

OUTPUT BUFFER CIRCUIT Referring now to FIG. 5, an output buffer circuit is schematically illustrated and includes an oscillator circuit 5 magnetically coupled through transformer 70 to an AC amplifier circuit 6. A decoupling unit 7 is provided and includes the static buffer shield 103 through which the ring core of transformer 70 is projected. The input terminals to the oscillator circuit 5 includes a triggering portion for the oscillator which is associated with terminals 502 and 503, and an oscillator- ;blocking portion associated with terminals 503 and 504.

The oscillator-triggering portion of the circuit 5 includes an AND gate circuit with diode 506 connected in series with the triggering terminal 502, a similarly poled diode 507 connected in series with the write-in terminal 503 and a voltage-dropping resistor 508 connected to the cathodes of diodes 506, 507. An

'N-P-N triggering transistor 510, having a base, b, an emitter, e,

and collector, c, has its base terminal connected to resistor 508. A biasing resistor 509 is connected between the base and emitter terminals of the triggering transistor 510. Aresistor 511 is connected between the positive DC input terminal 501 and the collector of transistor 510. A second resistor 512, connected between the cathode and emitter terminals of transistor 510, forms a voltage divider with resistor 511. A diode 515 is also connected to the collector terminal of trig gering transistor 510 and forms a series circuit with a primary winding 71 of transformer 70 and the collector-emitter junction of N-P-N oscillator-blocking transistor 534 when this junction is conductive. An N-P-N oscillator transistor 516 has its base connected directly to the collector of blocking transistor 534. The oscillator transistor 516 is emitter biased by a capacitor 517 in parallel with a resistor 518 connected to ground. A filter capacitor 520 is connected between the cathode of diode 515 and the emitter of transistor 516. A filter capacitor 519 is connected between the cathode of diode 515 and ground, and a filter capacitor 51 is connected between the anode of diode 515 and ground.

Oscillator elements, including a capacitor 521 and primary winding 72 of transformer 70, are connected in the collectoremitter circuit of oscillator transistor 516. The capacitor 521 and inductive winding 72 are connected in parallel between the collector of transistor 516 and a filter inductor 513 which is connected to the positive DC input terminal 501. The filter circuit for the oscillator elements includes inductor 513 and a capacitor 514 which is connected from the output of inductor 513 to ground.

A third primary winding 73 of transformer 70 is connected in series with a diode rectifier 522 across a filter capacitor 523 which is in parallel with resistor 524. The rectifier input voltage at the cathode of diode 522 is connected in a feedback circuit including a resistor 525 in series with a diode 526 to the cathode of-diode 515 and into the base of transistor 516 for producing continued oscillations.

Referring now to the oscillator blocking portion of oscillator circuit 5, and AND gate circuit is formed by diode 528 connected in series with the blocking-input terminal 504, a like poled diode 527 connected in series with the write-in terminal 503 and a voltage-dropping resistor 529 connected to the common cathode terminals of diodes 527 and 528. An N- P-N blocking transistor 530 has its base connected to resistor 529, and also has a resistor 531 connected between the base and emitter, the emitter being connected to ground. The collector of blocking transistor 530 is connected to the common connected cathode terminals of diodes 506, 507 and the collector isalso connected through voltage-dropping resistor 533 to the base of transistor 534. The collector of transistor 530 is also connected to resistor 532, and the resistor 532 is connected to the output of the filter inductor 513 to forward bias the collector-emitter junction of transistor 530. A resistor 535 is connected between the base and emitter of transistor 534, the emitter also being connected to ground.

The AC amplifier circuit 6 includes the secondary winding 74 of transformer 70 which is connected in series with a rectifying diode 601, the cathode of which is connected to a parallel resistor 602 and capacitor 603 for filtering the voltage induced in the secondary winding 74. The cathode of diode 601 is also connected to a voltage-dropping resistor 604 connected to the control electrodes of thyristors 605 and 606. The thyristors 605, 606 are part of a bridge circuit including the anode-cathode junction of thyristor 605 in series with the diode 610 and the anode-cathode junction of thyristor 606 in series with the diode 609. An AC voltage source 608 is connected between ground and anode of thyristor 60S, and a load 611 is connected between the anode of thyristor 606 and ground. The anode side of diode 601 is connected through the secondary winding 74 and is common to the cathodes of thyristors 605, 606 and also in common with the anodes of diodes 609, 610. A current limiting resistor 607 is connected from this common point to the commonly connected control terminals of thyristors 605, 606.

OPERATION OF OUTPUT BUFFER CIRCUIT The operation of the output buffer circuit illustrated in FIG. includes the following events for producing oscillations. Before oscillations have been initiated in circuit 5, triggering transistor 510 is maintained at saturation by a positive voltage being applied to both the triggering terminal 502 and the write-in terminal 503. Since the diodes 506 and 507 are forward biased by the application of the DC input voltages at these two terminals, the base of triggering transistor 510 is positive with respect to the emitter. A DC current flows through the resistor 511 and though the collector-emitter junction of triggering transistor 510 to ground causing the collector terminal of transistor 510 to be at ground potential. Oscillator transistor 516, therefore, has ground potential applied to its base terminal and, therefore, the collector-emitter junction of this transistor is essentially an open circuit. When the voltage applied to terminals 502 and 503 are both near or at zero, the base of triggering transistor 510 goes to zero, and this causes the collector-emitter junction of transistor 510 to be essentially an open circuit. The voltage across the collector-emitter tenninals of transistor 510 then becomes the voltage across resistor 512, and this voltage forward biases diode 515 which is in series with the primary winding 71 of transformer 70, and this applies a positive voltage to the base of transistor 516. When the base of the transistor 516 becomes positive with respect to its emitter, the collector-emitter junc tion of transistor 516 becomes conductive.

The changing current in primary winding 71 induces a current in primary winding 72 and causes oscillations of current in the collector-emitter circuit of transistor 516 which has been rendered conductive. The oscillations are sustained at the resonant frequency of the parallel circuit formed by capacitor 521 and the inductance of the primary winding 72.

The third primary winding 73 of transformer 70 also has an induced current flowing in it when the current changes in primary winding 71. This oscillating current is rectified by passing it through diode S22 and this charges filter capacitor 523. The rectified filtered voltage is then fed back through the series elements 325, 326 and added to the current input of the primary winding 71 in order to provide continued oscillations.

The current oscillations in the primary windings of transformer 70 are magnetically coupled to secondary winding 74. The decoupling unit 7, including the static buffer shield 103, isolates the primary circuit from the secondary circuit in the same way as described before for the input buffer circuit. The current oscillations induced in the secondary winding 74 are rectified by diode 601, filtered by resistor 602 and capacitor 603 and are applied to the control terminals of thyristors 605 and 606 simultaneously. When the AC source 608 is providing a positive half-cycle of voltage, the current flows through the anode-cathode junction of thyristor 605, through the common bridge connection, through the anode-cathode junction of diode 610 and into the load 61] to ground. When the AC source 608 is producing a negative half-cycle of voltage, the path of the current is through the load 611, from the anodecathode junction of thyristor 606, through the common bridge connection and through the anode-cathode junction of diode 609 and into the source 608.

The operation of the oscillator blocking portion of the circuit shown in FIG. 5 will be considered next. In order for oscillations to occur according to the above analysis of the oscillator action, it has been assumed that the blocking input terminal 504 has been maintained at a positive DC voltage level while the terminals 502 and 503 have been maintained near or at zero level. In order to block the oscillations, both terminals 503 and 504 must be brought near or at a zero level. When this is done, the voltage on the base of transistor 530 will be reduced to zero and the collector'emitter junction of transistor 530 will no longer be conductive. It should be understood that a positive signal applied to either the write-in terminal 503 or the blocking terminal 504 will maintain transistor 530 at saturation until both of the voltages are removed, and when transistor 530 is maintained at saturation, transistor 534 has its base terminal maintained at ground potential through the essentially short-circuited cathodeemitter junction of transistor 530. Also note that when transistor 530 is shut off, the voltage divider action of resistors 532 and S33 and 535 produces a positive voltage on the base of transistor 534 with respect to its emitter which then produces essentially a short circuit between the collectoremitter junction of transistor 534, and this action short circuits the base of oscillator-transistor 516 to ground. Thus, oscillator transistor 516 is shut off, and the oscillations are blocked.

FIG. 6 is a partial schematic illustration of the embodiment of FIG. 5 with the AC amplifier on the secondary side of the transformer replaced with a DC amplifier circuit. The same primary circuit of FIG. 5 is intended to be used as the primary circuit for FIG. 6.

The secondary winding 74 is connected in series with a rectifying diode 621 which has its cathode connected to a filter including resistor 622 in parallel with capacitor 623. A voltage-dropping resistor 624 is connected to the cathode of diode 621 and to the base of an N-P-N transistor 626. A bias resistor 625 is connected between the base and the collector of transistor 626, and the emitter terminal is also connected to the negative terminal 629 of a DC voltage source. The load 627 is connected between the positive terminal 630 of the DC voltage source and to the collector of transistor 626. A diode 628 is connected in parallel with the load with its anode connected to the collector of transistor 626. The diode 628 is used to absorb impulses of current when inductive loads are present. The operation of the demodulator circuit shown in FIG. 6, taken in conjunction with the primary side of the circuit of FIG. 5, is the same as the FIG. 5 operation with the exception that the rectified and filtered voltage of the secondary winding is applied to the base of a normally off transistor 626 to forward bias its collector-emitter junction thereby energizing a DC load 627.

Reference to FIG. 7 shows how the logic circuit boards 114 are mounted to the frame 116 of the Faraday cage by the use of mounting boards 115 with clamping guides 412 which clamp the edges of the circuit boards 114.

The invention has been described with reference to the preferred embodiments. Since certain changes may be made in the above construction without departing from the scope of the invention, it is intended that all matters contained in the above description and shown in the accompanying drawings shall be interpreted as illustrative and not limiting.

We claim:

1. A solid-state buffer circuit for decoupling interference, comprising:

oscillator circuit means for changing a DC input signal to an AC output signal;

demodulator circuit means for changing an AC input signal to a DC output signal;

means for magnetically coupling said AC output signal to the input of said modulator circuit means; and,

isolating means for creating a static interface between said oscillator circuit means and said demodulator circuit means, said isolating means including a Faraday cage having an aperture in a wall thereof in which said magnetic coupling mans is positioned to be magnetically isolated from said Faraday cage.

2. The buffer circuit of claim'l wherein a removably fixed metal plate substantially covers the aperture in the cage wall, said plate having a tongue-shaped element forming a U- shaped airgap communicating through the wall aperture, and

said magnetic coupling means includes a transformer, the core element of which is mated with said tongue element so that the diametral plane of the core element is normal to said plate through the airgap therein.

3. The buffer circuit of claim 2 wherein said isolating means further includes means for mounting one of said circuit means to the side of said plate facing outside said Faraday cage and proximate to said other circuit means mounted on a like mounting means to the side of said plate facing the inside of said Faraday cage.

4. The buffer circuit of claim 1 wherein a tongue-shaped element is formed in the plane of the wall conforming to the aperture having a U-shape, and said magnetic-coupling means includes a transformer, the core element of which is mated with the tongue element so that the diametral plane of the core element is normal to the cage wall through the aperture.

5. The buffer circuit of claim 4 wherein said isolating means further includes means for mounting one of said circuit means to the side of said wall facing outside said Faraday cage and proximate to said other circuit means mounted on a like mounting means to the side of said wall facing the inside of said Faraday cage.

6. In an automatic control system responsive to a process, the combination comprising:

input-oscillating circuit means initiated into oscillation by a change in the process;

input-demodulating circuit means magnetically coupled to said oscillating circuit means;

isolating means for creating a static interface between said input-oscillating circuit means and said input-demodulating circuit means;

processing circuit means within said isolating means, said processing circuit means connected to said input demodulating circuit means;

output-oscillating circuit means connected to said processing circuit means and isolated from said input oscillating circuit means by said isolating means; and

output-amplifying circuit means magnetically coupled to said output-oscillating circuit means through said isolating means to control the process.

7. The system of claim 6 wherein said isolating means includes a Faraday cage having a first aperture in a wall thereof through which said input-demodulating circuit means is magnetically coupled to said input-oscillating circuit means, and a second aperture through which said output-amplifying circuit means is magnetically coupled to said output-oscillating circuit meansv 8. The system of claim 7 wherein a removably fixed metal plate substantially covers each of the apertures in said cage wall, each said plate having a tongue-shaped element formed in a U-shaped airgap communicating through the wall aperture, and a transformer having a core element for magnetically coupling said respective circuit means is mated with the tongue-shaped element so that the diametrical plane of said core element is normal to said plate through the airgap therein.

9. The system of claim 8 wherein said isolating means further includes means for mounting said input-oscillating circuit means to the side of said plate facing outside said Faraday cage and proximate to said input-demodulating circuit means mounted on a like mounting means to the side of said plate facing the inside of said Faraday cage and said output-amplifying circuit means is mounted to a second plate on a like said mounting means facing outside Faraday cage and proximate to said output-oscillating circuit means mounted to said second plate on a like said mounting means facing the inside of said Faraday cage. 

1. A solid-state buffer circuit for decoupling interference, comprising: oscillator circuit means for changing a DC input signal to an AC output signal; demodulator circuit means for changing an AC input signal to a DC output signal; means for magnetically coupling said AC output signal to the input of said modulator circuit means; and, isolating means for creating a static interface between said oscillator circuit means and said demodulator circuit means, said isolating means including a Faraday cage having an aperture in a wall thereof in which said magnetic coupling mans is positioned to be magnetically isolated from said Faraday cage.
 2. The buffer circuit of claim 1 wherein a removably fixed metal plate substantially covers the aperture in the cage wall, said plate having a tongue-shaped element forming a U-shaped airgap communicating through the wall aperture, and said magnetic coupling means includes a transformer, the core element of which is mated with said tongue element so that the diametral plane of the core element is normal to said plate through the airgap therein.
 3. The buffer circuit of claim 2 wherein said isolating means further includes means for mounting one of said circuit means to the side of said plate facing outside said Faraday cage and proximate to said other circuit means mounted on a like mounting means to the side of said plate facing the inside of said Faraday cage.
 4. The buffer circuit of claim 1 wherein a tongue-shaped element is formed in the plane of the wall conforming to the aperture having a U-shape, and said magnetic-couPling means includes a transformer, the core element of which is mated with the tongue element so that the diametral plane of the core element is normal to the cage wall through the aperture.
 5. The buffer circuit of claim 4 wherein said isolating means further includes means for mounting one of said circuit means to the side of said wall facing outside said Faraday cage and proximate to said other circuit means mounted on a like mounting means to the side of said wall facing the inside of said Faraday cage.
 6. In an automatic control system responsive to a process, the combination comprising: input-oscillating circuit means initiated into oscillation by a change in the process; input-demodulating circuit means magnetically coupled to said oscillating circuit means; isolating means for creating a static interface between said input-oscillating circuit means and said input-demodulating circuit means; processing circuit means within said isolating means, said processing circuit means connected to said input demodulating circuit means; output-oscillating circuit means connected to said processing circuit means and isolated from said input oscillating circuit means by said isolating means; and output-amplifying circuit means magnetically coupled to said output-oscillating circuit means through said isolating means to control the process.
 7. The system of claim 6 wherein said isolating means includes a Faraday cage having a first aperture in a wall thereof through which said input-demodulating circuit means is magnetically coupled to said input-oscillating circuit means, and a second aperture through which said output-amplifying circuit means is magnetically coupled to said output-oscillating circuit means.
 8. The system of claim 7 wherein a removably fixed metal plate substantially covers each of the apertures in said cage wall, each said plate having a tongue-shaped element formed in a U-shaped airgap communicating through the wall aperture, and a transformer having a core element for magnetically coupling said respective circuit means is mated with the tongue-shaped element so that the diametrical plane of said core element is normal to said plate through the airgap therein.
 9. The system of claim 8 wherein said isolating means further includes means for mounting said input-oscillating circuit means to the side of said plate facing outside said Faraday cage and proximate to said input-demodulating circuit means mounted on a like mounting means to the side of said plate facing the inside of said Faraday cage and said output-amplifying circuit means is mounted to a second plate on a like said mounting means facing outside Faraday cage and proximate to said output-oscillating circuit means mounted to said second plate on a like said mounting means facing the inside of said Faraday cage. 